VERILOGHDL 8位串行乘法器解析（二）
关于8位串行乘法器的缺点，书上也提到过慢。 具体分析一下串行乘法器的硬件结构，即逐级进位信号的传输带来的延迟。 对于 8 位串行乘法器，请参见下面的仿真图。在这里，作者特意将乘法器和被乘数这2个变量设置为8个时钟周期，这样我们就可以清楚的看到并推断出N位串行乘法器由于其移位操作需要移位。 ，会有N个时钟延迟，所谓慢。
另外需要注意的是，与C/C++语言类似，需要给出count变量（本例中用count计数8个时钟周期）和状态变量（在case语句中不同情况下使用） 初始值，否则会发生不可预知的错误。 仿真代码如下，供参考：
module ade_test;
// Inputs
reg clk;
reg x;
reg y;
// Outputs
wire p;
// Instantiate the Unit Under Test (UUT)
ade uut (
.clk(clk),
.x(x),
.y(y),
.p(p)
);
parameter clk_period = 20;
initial begin
// Initialize Inputs
clk = 0;
x = 0;
y = 0;
// Wait 100 ns for global reset to finish
//#100;
// x = 2;
//y = 3;
// Add stimulus here
end
always # (clk_period/2) clk = ~clk;
always # (clk_period*8) x = (x+3) % 10;
always # (clk_period*8) y = (y+1) % 15;
endmodule
(The disadvantages of 8-bit serial multiplier are also mentioned in the book. Specifically analyze the hardware structure of the serial multiplier, that is, the delay caused by the transmission of the carry signal step by step. For the 8-bit serial multiplier, see the simulation diagram below.
Here, the author specially sets the two variables of multiplier and multiplicand to 8 clock cycles, so that we can clearly see and infer that the N-bit serial multiplier needs to be shifted due to its shift operation, There will be n clock delays, called slow.
In addition, it should be noted that, similar to C / C + + language, it is necessary to give the initial values of count variable (count is used to count 8 clock cycles in this example) and state variable (used in different cases of case statement), otherwise unpredictable errors will occur. The simulation code is as follows for reference:
module ade_ test;
// Inputs
reg clk;
reg x;
reg y;
// Outputs
wire p;
// Instantiate the Unit Under Test (UUT)
ade uut (
.clk(clk),
.x(x),
.y(y),
.p(p)
);
parameter clk_ period = 20;
initial begin
// Initialize Inputs
clk = 0;
x = 0;
y = 0;
// Wait 100 ns for global reset to finish
//#100;
// x = 2;
//y = 3;
// Add stimulus here
end
always # (clk_period/2) clk = ~clk;
always # (clk_period*8) x = (x+3) % 10;
always # (clk_period*8) y = (y+1) % 15;
endmodule
)
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